Vweb Chip Sails Through Verification Half the Normal Time Using Axis' Xcite Simulation Acceleration System

By Dr. Sho Long Chen

President and CEO

Vweb Corporation

San Jose, CA

To overcome the slow speed of software simulation for verifying Vweb’s MPEG2 encoder design, we turned to a relatively new type of hardware acceleration solution developed by Axis Systems. In addition to cutting total functional verification time in half, the acceleration system allowed us to verify more corner cases than software simulation would allow. As a result, we found more bugs than would otherwise have been possible and got the MPEG2 chip to market three months earlier than expected.

Vweb’s VLAN Encoder is a third-generation MPEG2 encoder chip that takes advantage of our 10 MPEG algorithm patents in motion estimation, rate control and system-on-a-chip technology. The chip compresses progressive video into MPEG2 digital video with bit rates ranging from 2 to 15 Mbps. Resolution can range up to 720x480 (NTSC) or 720x576 (PAL), suiting the chip for use in high-quality PC-based MPEG Camera -eCAM, Web Artist –eVA box, Digital Video Recorder – eZIP and  a variety of other network-based video over IP applications - eVIP.

At 500k gates, the VLAN Encoder has the smallest die size of any MPEG2 chip on the market and uses the least power. The key to the VLAN Encoder’s small size is its use of motion estimation and rate control (Figure 1), which enable the chip to detect the differences between successive video frames in the frequency domain and use that information to encode the frames with little hardware overhead. At the same time, the encoding algorithms maintain high image quality—with only 0.25 dB difference in Signal to Noise Ratio compared to that of ISO MPEG encoder and Vweb’s encoder video quality is better than the best competing encoder.

The verification challenge

The goal in verifying the VLAN Encoder was to ensure high quality by evaluating as many corner cases as possible. Meeting that goal required the simulation of thousands of video frames, but software simulators simply cannot deliver high enough speed to make such simulations practical. Even when verifying a single 50k-gate module for the chip, a software simulator took 4 days to execute the processing of 150 video frames. We clearly required a faster alternative.

How fast is fast enough? Everyone wants simulations to run as fast as possible, but it is important to keep in mind that the hardest task in verification is to find the bugs and diagnose the problem once a bug has been found. A verification solution that supports easy debug can save more time overall than a blazingly fast emulation system that is hard to use. For the same reasons, we wanted a solution that required minimal overhead work. Setup time had to be short, and the ongoing configuration effort had to be as easy as possible. Vweb’s focus as a young start-up company had to be on getting product to market and not on EDA tool support.

Thus, the first step in evaluating acceleration solutions was to see how long it took to set up the system. Specifically, we wanted a solution that took no more than 2 weeks for set up. Vweb engineers evaluated three systems—a hardware accelerator, an emulator, and the Axis acceleration system mentioned earlier. After two weeks of set up work to simulate one module, the Axis Xcite 1000 system was up and running, but neither of the other systems was ready. The other systems also cost far more than the Axis solution and had additional drawbacks, so we went with Axis.

Speed plus easy debug

The Axis system gave us more than 70X faster simulation speed than our software simulator. The 150-frame RTL simulation that took many days to run in software took just hours on the Axis system. When simulating the entire MPEG2 encoder design in RTL, the Axis system took minutes per frame compared to many hours per frame for software simulation.  

This speed allowed us to run an enormous number of corner cases that would have been impossible to examine with a software simulator. A typical simulation run included 1000 video sequences, each consisting of 60 frames. These tests allowed us to find bugs such as Skip Micro Block at the end of slice. The Axis system also resolves the Don’t Care conditions that show up in Verilog simulations.

 An Axis tool called VCD-on-Demand proved valuable in helping us find the bugs. This tool captures all the activity generated by a simulation run in an extremely compact file. Users can then examine any internal nodes for any time sequence associated with a problem without rerunning the simulation. This capability allowed us to view the VCD results as though they were generated by the software simulator, making debug easy and freeing the Axis acceleration hardware for other tasks.

 Fitting into the design flow

Vweb’s design flow begins with customer requirements, architecture planning and C model development. The C models allow us to analyze bandwidth performance and compare video quality with industry standards. We then go to behavioral coding in Verilog, followed by synthesis with Design Compiler. We also use Prime Time and Power Compiler because timing and power considerations are critical for MPEG encoding in digital entertainment applications. We outsource the Placement and Routing,

BIST, Boundary Scan and Full Scan test generation to the third party design services.

We then do the Back-Annotation in house with complete test suites for verification.

The Axis system fit perfectly into this flow because it works with synthesizable RTL code. Rather than use the structure of FPGAs directly for emulation, Axis configures FPGAs as ReConfigurable Computing (RCC) elements. Each RCC handles a single instruction that closely follows RTL constructs, which makes debug easier by preserving the relationship between the original code and the simulation. Users simply see simulation results in a familiar software simulation environment—except that the results are available much faster than software simulation could provide.

Axis tools automatically compile the RTL code into the hardware accelerator. Compiling our RTL code into the system took about an hour using eight FPGA compiler licenses. While we can wish that the compilation time were shorter, the overhead is worthwhile given the overall speed improvement. We also have hopes that an incremental compile function now offered by Axis will shorten the compile time when we have only a few changes to make to our RTL code.

Overall, the Axis system gave us over 70X performance compared to software simulation. Our ability to see the activity on internal nodes also cut debug time. At Vweb, we know how important time to market is, so we enjoy that speed! We were able to slash our verification time from 6 months to just 3 months, and we analyzed more corner cases than we ever could have with software simulation. We plan to use the Axis system on all future designs.