Accelerator gives Vweb a four-month boost

By Richard Goering, EEdesign
Aug 8, 2000 (7:33 AM)
URL: http://www.eedesign.com/story/OEG20000808S0005

ms. The Xcite product employs the company's ReConfigurable Computing (RCC) engine and comes with a software Verilog simulator. More recently, Axis has rolled out Xtreme, which combines emulation with simulation.

Video compression chA relative newcomer in the hardware-assisted verification market, Axis Systems is promoting its Xcite-1000 accelerator as an easy-to-use alternative to more expensive emulation and acceleration systeipmaker Vweb is a satisfied user of the Xcite-1000. In this interview, Sho Long Chen, Vweb president and CEO, discusses how the accelerator shaved four months off the design cycle for an MPEG2 encoder chip. She notes, however, that Axis' strictly functional, two-state simulation doesn't solve all of Vweb's verification challenges.

EEdesign: What chip did you tape out using Axis' Xcite-1000?

Chen: It's an MPEG2 video compression chip. The total gate count is around 500K gates, and the die is 7.44 mm by 6.8 mm. Right now it's running at 108 MHz. Our main focus is video over IP. We can take frame video for Internet applications and go down to something like 128 Kbits per second.

EEdesign: What verification challenges did the chip pose?

Chen: Video always takes a long time. For verification, we need to pass all the sets of a video bitstream. Each set has about 150 frames. To run a sequence of 150 frames would take ten days, or two weeks, on [Cadence Design Systems] NC Verilog. With Axis it only took us 8 hours to run through one sequence of 150 frames.

Some of the bitstreams are very high speed. Some are very slow speed, but very fine resolution. Some involve different angles and colors. We need to verify all of the contents.

EEdesign: What was your verification flow before bringing in Axis?

Chen: We basically ran a C model, and then NC Verilog. After that we did logic synthesis using Synopsys, then used Synopsys Primetime to verify the setup and hold times. We ran Verilog gate-level simulation and compared that to RTL. After timing we sent out to place and route, generated SDF delay files, and ran the gate-level simulation again.

EEdesign: Why did you pick the Axis Xcite system?

Chen: I looked at three tools — Quickturn's Mercury emulator, Ikos' logic accelerator, and Axis. I gave everybody two weeks to get up and running. I gave them two test benches — one was a small module of 50K gates, and one was the whole chip. Only Axis was able to pass both of them.

Cost is also important to us. With Quickturn, it would be a minimum of $1 million. With Axis, maybe a quarter of that.

EEdesign: Does the Xcite system replace NC Verilog completely?

Chen: The majority of the work, 95 percent, is done by Axis. But I still need to run NC Verilog to make sure "don't cares" are taken care of. There are a lot of "don't cares" in RTL code. But with Axis you have to be very clear, because there is no unknown [X] state. Everything is either one or zero. If you don't set it, it will default to high or low.

EEdesign: How's the debugging capability of the Axis product?

Chen: The debugging is very good, especially when you run a long sequence, because you can stop at any point to go back to some other node. This is the feature called "VCD on demand" and it's the thing I like the best. It means you can view an internal node without rerunning the whole simulation.

EEdesign: How fast is the Xcite-1000?

Chen: We have a test module that we ran ourselves. At the gate level it's 70 times faster than NC Verilog on a Sun Solaris with a 400 MHz CPU. RTL speed is 28 times faster. For example, with NC Verilog it took 4 days to run 155 sequences. With Axis it took four hours.

EEdesign: But wouldn't an emulator be much faster?

Chen: Of course. An emulator runs at 1 MHz. But emulators haven't improved for the last 10 years.

EEdesign: How much time did the Xcite-1000 save you with the MPEG2 encoder chip?

Chen: I think we saved four months in verification. And, it was more thoroughly verified. Because of the speed we were able to run more sequences, and verify important parameters like baud rate and resolution.

EEdesign: Did you find problems you might not have found with software simulation alone?

Chen: Yes. An example would be a skipped macro block at the end of a sequence. You have to run through a long sequence to find that kind of bug.

EEdesign: Compilation times are often a bottleneck for accelerators. What kinds of compilation times have you observed with the Axis system?

Chen: With eight licenses, a 500K gate module took us one hour. With 16 licenses running on 16 workstations or PCs, we can reduce the hour to 40 minutes. We have eight licenses right now and are upgrading to 16. Also, they are adding a new incremental compilation feature. With a small change that affects only one or two FPGAs, that can reduce the compile time to less than 20 minutes on two workstations.

EEdesign: Anything you'd like to see improved with the Xcite system?

Chen: Definitely. I'd like to see the incremental compilation become faster and more robust. Number two, there's no timing information. It's only functional simulation. If they could take care of timing, I think that would be great. Finally, I think "don't cares" are important.